1. Field of the Invention
The present invention relates to an input circuit to which a first input signal and a second input signal are inputted from two input terminals and which outputs an output signal acquired by performing differential amplification of the first input signal and the second input signal from an output terminal. The present invention particularly relates to an input circuit which has a wide band of frequency characteristic and a large voltage range for input, with a high input impedance.
2. Description of the Related Art
The input circuits for the electronic measurement apparatuses, including an oscilloscope, need a so-called buffer amplifier for buffering to be less affected by the measured system (e.g., refer to JP-B-7-67053 and Japanese Patent No. 3154459). Particularly, in the case of an input circuit used in the oscilloscope, it is required to perform the offset adjustment for changing the voltage level of a DC (Direct Current) signal in a measuring signal so that the voltage range of the measuring signal from the measured system falls within the voltage range that can be treated by the input circuit and following circuits. The offset adjustment is implemented by providing the input circuit with a differential amplification circuit.
Also, it is required that the input circuit has a high input impedance to have no influence on the measured system. That is, it is required that the voltage of the measured system is only detected to keep the current flowing from a measured object into the input circuit. This is implemented by using a Field Effect Transistor (FET) at the first stage of the differential amplification circuit.
FIG. 3 is a block diagram of a conventional input circuit, and FIG. 4 is a circuit diagram of the input circuit as shown in FIG. 3. In FIGS. 3 and 4, an input terminal Ti1 is one input terminal of the input circuit, to which a measuring signal (first input signal) is applied from the measured system. An offset adjustment circuit 10 outputs an offset signal (second input signal). An input terminal Ti2 is the other input terminal of the input circuit, to which the offset signal is applied. A differential amplification circuit 20 has two inputs and one output, in which the measuring signal from the input terminal Ti1 is inputted into one input side and the offset signal (normally a DC signal) from the input terminal Ti2 is inputted into the other input side. And a signal corresponding to a voltage difference between the measuring signal and the offset signal is outputted from the output side to an output terminal To. The output terminal To is for the input circuit. A preamplifier circuit 30 is a circuit provided at the latter stage of the input circuit, with the input side connected to the output terminal To.
The differential amplification circuit 20 will be described below in detail.
A p-channel MOS-FET Q1 has the source connected via a constant current source Is to a power cable Vcc at a predetermined voltage level, and the drain connected to a power cable Vee at a predetermined voltage level. Also, the gate of the FET Q1 is one input end connected to the input terminal Ti1.
A p-channel MOS-FET Q2 has the source connected via a constant current source Is′ to the power cable Vcc at the predetermined voltage level, and the drain connected to the power cable Vee at the predetermined voltage level. Also, the gate of the FET Q2 is the other input end connected to the input terminal Ti2.
A differential signal/single end signal converter 21 is connected to the source of FET Q1, Q2, and converts a differential signal into a single end signal which is outputted via the output terminal To to the preamplifier circuit 30.
The operation of the above circuit will be described below.
A measuring signal from the measured system is inputted via the input terminal Ti1 into the gate of the FET Q1 in the differential amplification circuit 20. On the other hand, an offset signal of desired voltage level is inputted from the offset adjustment circuit via the input terminal Ti2 to the gate of the FET Q2 in the differential amplification circuit 20.
And a voltage following the voltage applied to each gate of the FET Q1, Q2 appears at the source of the FET Q1, Q2. Thus, the differential signal/single end signal converter 21 outputs a single end signal that is a voltage of the measured signal subtracted (or added) by a voltage of the offset signal via the output terminal To to the preamplifier circuit 30.
JP-B-7-67053 (pages 1 to 3, FIGS. 1 and 2) and Japanese Patent No. 3154459 (pages 1 and 2, FIG. 3) are referred to as related art.
Thus, the differential amplification circuit 20 has a high input impedance by using the FET Q1, Q2 at the first stage. Also, the frequency (so-called frequency characteristic) of the differential amplification circuit 20 to be transferred to the preamplifier circuit 30 at the latter stage is limited by the FET Q1, Q2. This frequency characteristic is typically about several hundreds [MHz].
However, in the case of measuring the high frequency signal (e.g., at least 1 [GHz]) with the oscilloscope, the differential amplification circuit 20 was difficult to transfer the high frequency signal to the preamplifier circuit 30 correctly.
If the FET Q1, Q2 are manufactured as the ordered products by altering the semiconductor design or manufacturing method of the FET Q1, Q2, the frequency characteristic may be enhanced. However, the rated range of input voltage (i.e., voltage range of FET Q1, Q2 into the gate) is narrowed. Therefore, the adjustment for large offset amounts could not be made to narrow the voltage range of measuring signal.